Fabrication of magneto-resistive devices normally involves a sequence of processing steps during which many layers of metals and dielectrics are deposited and then patterned to form a magneto-resistive stack as well as electrodes for electrical connections. The magneto-resistive stack usually includes the free and pinned layers of the device, sandwiched around one or more dielectric layers functioning as the tunnel junction for the magnetic tunnel junction (MTJ) device.
A critical challenge in magnetic randam access memory (MRAM) technology is the patterning of the magnetic tunnel junction (MTJ) stack without damaging the device. The thin magnetic layers used in the MTJ stack, are easily damaged during plasma etch processes. Therefore a processing scheme for manufacturing the MTJ device that can minimize the exposure of the tunnel junction to plasma processes is desired.
U.S. Pat. No. 6,849,465 (Park et al) and U.S. Pat. No. 9,373,782 (Li et al) teach patterning the bottom electrode first, then depositing and patterning the MTJ stack, but these methods are different from the present disclosure.